Division, in binary arithmetic, is generally accomplished by successive shift and subtract operations. The number to be divided is known as the dividend (DD), while the number by which the DD is divided is known as the divisor (DR). Binary division is simpler than decimal division because there is no need to estimate how many times the DR fits into the DD or the partial remainder (PR) since binary digits (bits) can assume only the values "zero" or "one."
There are several techniques for performing binary division--these include both sliced and non-sliced designs. In a typical non-sliced design, division is accomplished as follows: an n-bit DR is compared to the most significant n bits of an m-bit DD, where n.ltoreq.m. If the most significant n bits of the DD represent a number smaller than the number represented by the n-bit DR, a "zero" is deposited in the quotient register (Q-register) in the bit position corresponding to the (n-1)th bit from the left most (most significant) bit (MSB) and the DD is shifted, relative to the DR, one bit position to the left. Again, a comparison is made. This time, however, the n-bit DR is compared to the most significant n+1 bits of the m-bit DD. Should the DR again be smaller, a "zero" w-11 be deposited in the Q-register bit position immediately to the right of the last deposited bit therein.
However, should the DR be greater than or equal to the number to which it is being compared, the DR is subtracted from the portion of the DD in question leaving what is referred to as a partial remainder (PR). Moreover, a "one" is deposited in the Q-register immediately to the right of the last deposited bit.
This process is repeated with the DR being compared to the PR. If the PR is greater than or equal to the DR, the bit deposited in Q-register is a "one" and a new PR is computed from the subtraction of the DR from the old PR; else, no subtraction is done and a "zero" is deposited in the Q-register. In either case, the PR is left-shifted to become the new PR. Each repetition is known as an "iteration". At the end of any iteration, the results of the division to that point in time can be found in Q-register with the remainder in PR. The process may continue until each bit in Q-register has been deposited with a "one" or "zero."
The process just described is known as the "comparison" method of binary division. Another method of binary division is known as the "non-restoring" method. In the non-restoring method, the DR is subtracted from the DD/PR regardless of the relative magnitude of DR and DD/PR. Should the result of the subtraction be greater than or equal to zero, a "one" is deposited in the Q-register. However, should the subtraction yield a result less than zero, a "zero" is deposited in Q-register and the next iteration of the division will perform the addition of the DR to the DD/PR. In either event, after each subtraction or addition, the DD/PR is shifted one bit to the left.
The binary division techniques referenced above, as well as others, can be implemented in a "bit-sliced" fashion.
In a bit-sliced design configuration, at least several of the most significant bits of the DD are located in a "master" slice while the remaining bits are parsed among one or more "slave" slices. Each individual slice takes the form of an individual divider as described above. Bit-sliced divider designs are sometimes preferred over non-sliced binary division schemes.
In bit-sliced binary division, each iteration of the division process is parsed into the iterations of the separate slices. That is, a given iteration of a non-sliced divider is equivalent to a combination of the separate iterations of the several individual slices. Moreover, the completion of the current master slice iteration triggers the current iteration of the slave slices. The master slice will not perform its next iteration until all the slave slices finish their current iteration.
The problem with bit-sliced binary division is that the master slice must communicate with each slave slice so as to inform each slave slice whether to perform a subtraction or addition with its "slice" of the DD and the DR. That is, no slave slice can function until after the master slice performs its task of either adding or subtracting the DR. Moreover, since in sliced-designs the master slice requires data from a slave slice, as described below, the master slice must wait until the slave slice is finished processing and ready to return the required data. At best, this introduces a two processing cycle delay in each iterative step in the division process.